1. Field of the Invention
The present invention relates to a backlight control circuit and, more particularly, to a backlight control circuit which controls a backlight used as a light source in a liquid crystal display, a backlight device equipped with the backlight control circuit, and the liquid crystal display including the same.
2. Description of the Related Art
In general, there is a continual need for liquid crystal displays (“LCDs”) which have lighter weight, slimness and low power consumption requirements. Since the LCD is a non-emissive device, a separate light source is necessary, however. As a result, a cold cathode fluorescent lamp (“CCFL”) or, alternatively, a backlight unit which includes light emitting diodes (“LEDs”) has been used as the separate light source in the LCD.
FIG. 1 is a block diagram of a liquid crystal display of the prior art.
The liquid crystal display 1 of the prior art includes a controller 2 including a timing control circuit 3 and a control logic circuit 4, a backlight control unit 5, a backlight unit 6 and a liquid crystal display panel 7.
The timing control circuit 3 controls transmission timing to transmit digital video data corresponding to a video signal from an external circuit to circuits provided after the control logic circuit 4.
More specifically, the control logic circuit 4 generates the digital video data corresponding to the video signal to transmit the digital video data to the backlight control unit 5 and the LCD panel 7 based on the transmission timing set by the timing control circuit 3. In addition, the control logic circuit 4 generates a vertical synchronization signal, a horizontal synchronization signal, a clock signal and a load signal, for example, (described in greater detail below with reference to FIG. 2) to output the abovementioned signals to the backlight control unit 5 based on the transmission timing set by the timing control circuit 3.
The backlight control unit 5 generates an internal load pulse signal data.o, and a pulse width modulation (“PWM”) pulse signal which is used to locally control a brightness of a plurality of light sources provided inside the backlight unit 6, based on the vertical synchronization signal, the horizontal synchronization signal, the clock signal and the load signal, for example, which are provided from the control logic circuit 4. The backlight unit 6 includes a plurality of LEDs (not shown) as the plurality of light sources, and the brightness of the plurality of light sources is locally controlled by the PWM pulse signal input from the backlight control unit 5.
The LCD panel 7 includes a thin film transistor (“TFT”) liquid crystal panel (not shown) to display an image, e.g., a video image, in response to the digital video data input from the control logic circuit 4.
FIG. 2 is a block diagram which illustrates connections between a control logic circuit of the prior art and a backlight control unit of the prior art.
Referring to FIG. 2, the control logic circuit 4 is electrically connected to the backlight control unit 5 through five external interconnections therebetween. The five external interconnections serially transmit a vertical synchronization signal v.sync, a horizontal synchronization signal h.sync, a serial transmission clock signal CLK, a digital video data DT and a load signal LD from the control logic circuit 4 to the backlight control unit 5. The backlight control unit 5 may include a plurality of backlight control circuits 5a to 5j (described in greater detail below with reference to FIG. 4).
FIG. 3 is a block diagram of an internal structure of a backlight control circuit of the prior art.
Referring to FIG. 3, a backlight control circuit 5a includes a shift register 51, a buffer register 52, a plurality of data registers 53a to 53f, a plurality of PWM generators 54a to 54f, a counter/decoder 55 and an oscillator 56.
The shift register 51 stores the digital video data DT at predetermined timing interval based on the serial transmission clock signal CLK. The buffer register 52 transmits the digital video data DT, which has been stored in the shift register 51, to data registers 53a to 53f of the plurality of data registers 53a to 53f, connected in electrical parallel with each other, at a timing set by the load signal LD. The counter/decoder 55 counts a number of pulses of the horizontal synchronization signal h.sync input as a clock signal clk, and transmits a decoding signal 1d obtained by decoding a count value of the abovementioned number of pulses to the data registers 53a to 53f. In addition, the counter/decoder 55 receives the vertical synchronization signal v.sync as a reset pulse rst to initialize the count value. The oscillator 56 receives the vertical synchronization signal v.sync from the counter/decoder 55, generates a reference clock signal clk2 used to generate PWM pulse signals PWM0 to PWM5 corresponding to the digital video data DT loaded into the data registers 53a to 53f, respectively, and provides the reference clock signal clk2 to PWM generators 54a to 54f of the plurality of PWM generators 54a to 54f. The data registers 53a to 53f load the digital video data DT from the buffer register 52 at the timing of the decoding signals 1d transmitted from the counter/decoder 55. The PWM generators 54a to 54f generate the PWM pulse signals PWM0 to PWM5, respectively, which correspond to the digital video data DT loaded into the data registers 53a to 53f, respectively, based on the reference clock signal clk2 provided from the oscillator 56.
FIG. 4 is a block diagram of an internal structure of a backlight control unit of the prior art including the backlight control circuit 5a of the prior art shown in FIG. 3.
Referring to FIG. 4, the backlight control unit 5 includes the plurality of backlight control circuits 5a to 5j, as described above. The backlight control circuits 5b to 5j of the plurality of backlight control circuits 5b to 5j each have a structure substantially the same as shown in FIG. 3 and described in greater detail above. The backlight control unit 5 classifies, e.g., groups or divides, light sources of the plurality light sources inside the backlight unit 6 into 10×8 local blocks, for example, to control brightness of each of the local blocks. Further, in the backlight control unit 5, the backlight control circuits 5a to 5j each have eight output lines to output the PWM pulse signals, and are electrically connected to each other through five signal lines to transmit respective signals (the vertical synchronization signal v.sync, the horizontal synchronization signal h.sync, the serial transmission clock signal CLK, the digital video data DT and the load signal LD associated with each of the backlight control circuits 5b to 5j, for example). In the backlight control unit 5, the backlight control circuits 5a to 5j perform a local dimming control. More specifically, the backlight control circuits 5a to 5j output the PWM pulse signals to control turn-on/turn-off operations of the light sources provided inside the backlight unit 6 by classifying the light sources into the 10×8 local blocks, and to control the brightness of each of the light sources by controlling the brightness of each of the local blocks.
In addition, the liquid crystal display 1 transmits approximately 100 (one hundred) 10-bit digital video data corresponding to the video signal for every one frame (e.g., for every approximately 16.7 ms to approximately 8.3 ms, depending upon a frame rate of the liquid crystal display). Accordingly, approximately one hundred 10-bit digital video data are serially transmitted between the control logic circuit 4 and the backlight control unit 5 (FIG. 2) for every one frame. However, the control logic circuit 4 and the backlight control unit 5 in the liquid crystal display of the prior art are mounted on different printed circuit boards (“PCBs”). As a result, external interconnections connecting the different printed circuit boards to each other are required. Further, a serial transmission scheme is thereby required to reduce a number of the external interconnections.
Referring again to FIGS. 1 to 4, the backlight control unit 5 generates the PWM pulse signals according to the digital video data DT corresponding to the video signal based on the reference clock signal clk2, which is generated from the oscillator 56 included in each backlight control circuit 5a to 5j, and the brightness of the light sources of the backlight unit 6 is controlled by local blocks in response to the video signal. The reference clock signal clk2 generated from the oscillator 56 is different from the vertical synchronization signal v.sync used to transmit the video signal. Accordingly, a timing to control the display of a video is asynchronous with respect to a timing to control the brightness of the backlight unit 6. As a result, a quality of a video displayed on the LCD panel 7 is degraded.
Accordingly, in order to avoid such an asynchronous state, an additional circuit such as a phase locked loop (“PLL”) circuit is required in the backlight control unit 5 of the prior art to correct a synchronization time difference between the reference clock signal clk2 and the vertical synchronization signal v.sync. However, such an additional component, e.g., the PLL, provided in the backlight control unit 5 increases a manufacturing cost of the backlight control unit 5 of the prior art. Further, the additional component increases a manufacturing cost of a backlight device including the backlight control unit 5 and a liquid crystal display including the backlight device.
As shown in FIG. 2, the control logic circuit 4 is connected to the backlight control unit 5 through the connections therebetween. A reduction of a number of the interconnections between circuit blocks is a very important factor considered in circuit design. Accordingly, it is also desired to reduce a number of external interconnections connecting the control logic circuit 4 to the backlight control unit 5.